According to an electrically rewritable non-volatile memory called EEPROM (Electrically Erasable Programmable ROM), since one bit is constructed by two transistors, an occupation area per bit is large and there is a limitation in case of raising an integration degree. To solve such a problem, a flash memory in which one bit can be realized by one transistor by an all-bit batch erasing method has been developed. The flash memory is expected as a memory which can be substituted for a recording medium such as magnetic disk, optical disk, or the like.
It is known that a memory card having a flash memory is constructed so as to be detachable to/from an apparatus. By using such a memory card, a digital audio recording and reproducing apparatus using the memory card in place of the conventional disk-shaped medium such as CD (Compact Disc), MD (Minidisc), or the like can be realized. Besides audio data, still image data and motion image data can be also recorded into the memory card and it can be used as a recording medium of a digital still camera or a digital video camera.
According to the flash memory, a data unit called a segment is divided into a predetermined number of clusters (fixed length) and one cluster is divided into a predetermined number of sectors (fixed length). The cluster is also called a block. The sector is also called a page. In the flash memory, an erasure is performed in a lump on a cluster unit basis, and the writing or reading operation is performed in a lump on a sector unit basis.
For example, in case of the flash memory of 4 MB (megabytes), as shown in FIG. 12, one segment is divided into 512 clusters. The segment is a unit for managing a predetermined number of clusters. One cluster is divided into 16 sectors. One cluster has a capacity of 8 kB (kbytes). One sector has a capacity of 512 B. A memory of a capacity of 16 MB can be constructed by using four segments each having a capacity of 4 MB.
As shown in FIG. 13A, logic cluster addresses are allocated to a memory space of 16 MB. The logic cluster address is set to a length of 2 bytes in order to distinguish 512×4=2048 clusters. In FIG. 13A, the logic cluster address is expressed by a hexadecimal number. 0x denotes the hexadecimal notation. A logic address is an address which is logically handled by a data processing apparatus (software). A physical address is added to each cluster in the flash memory. A correspondence relation between the clusters and the physical addresses is unchanged.
According to the flash memory, by rewriting data, an insulating film deteriorates and the number of rewriting times is limited. Therefore, it is necessary to prevent a situation such that accesses are repetitively and concentratedly performed to a certain same memory area (cluster). Therefore, in case of rewriting data in a certain logic address stored in a certain physical address, in a file system of the flash memory, updated data is not rewritten to an unused cluster. Thus, the correspondence relation between the logic addresses and the physical addresses before the data updating changes after the updating. By performing such a swapping process as mentioned above, the situation such that the accesses are repetitively and concentratedly performed to the same cluster is prevented, so that a life of the flash memory can be extended.
Since the logic cluster address is accompanied by the data which has once been written into the cluster, even if physical cluster addresses in which the data before updating and the data after the updating are written are changed, the same address is seen from a file management system and the subsequent accesses can be properly performed. Since the correspondence relation between the logic addresses and the physical addresses is changed by the swapping process, a logical/physical address conversion table showing the correspondence between them is needed. By referring to such a table, the physical cluster address corresponding to the designated logic cluster address is specified, thereby enabling the access to the cluster shown by the specified physical cluster address to be performed.
The logical/physical address conversion table is stored in a memory by the data processing apparatus. If a memory capacity of the data processing apparatus is small, the table can be stored in the flash memory. FIG. 13B shows an example of a logical/physical address conversion table regarding segment 1. As shown in FIG. 13B, in the logical/physical address conversion table, the physical cluster addresses (2 bytes) are made to correspond to the logic cluster addresses (2 bytes) arranged in the ascending order, respectively. The logical/physical address conversion table is managed every segment and its size increases in accordance with the capacity of the flash memory.
There is a case where it is desirable to set a data writing speed to be higher than the ordinary one by making a plurality of storages of the flash memory operative in parallel. For example, an electronic music distribution EMD for distributing music data through a network is being put into practical use. The distributed music data is stored into a hard disk of a personal computer, data of a desired music piece is copied or moved into a memory card by the personal computer, and the memory card is attached into a portable recorder, so that the user can easily listen to the desired music at a place other than his home. Data of a plurality of music pieces is downloaded into the memory card from the hard disk by a parallel writing operation (at a high speed) and, upon reproduction, the music data is read out from the memory card at a normal speed.
FIG. 14 shows a construction of a conventional logic address for four storages. In the example of the diagram, address spaces in the memory are expressed by 11 bits of A0, A1, . . . , and A10. A0 denotes the LSB (least significant bit) and A10 indicates the MSB (most significant bit). The storages each having a capacity of 4 MB are switched by the MSB (A10) and the second MSB (A9). Addresses of 9 bits of A0 to A8 are allocated to a sector and a segment in each storage.
When data is written, the operation is executed at a timing as shown in FIG. 15. First, the data is transferred from the host side to a page buffer of a sector size. Time T is required to transfer. In a next write busy period, the data is transferred from the page buffer into a flash buffer in the flash memory and the data is written into the storage.
Upon reading, as shown in FIG. 16, the data is read out from the flash memory for a read busy period. The read-out data is transferred to a page buffer of a sector size. In the next transfer time T, the data is transferred from the page buffer to the host side.
FIG. 17 is a flowchart showing a flow of processes in case of writing data into continuous logic sectors 0 to 3 belonging to different clusters in a certain segment. In first step S11, a logical/physical conversion table is formed with respect to a segment as a target to be written. In step S12, sector 0 is sent from the host side. The time T is required for this transfer. In step S13, sector 0 is written into the flash memory. In step S14, sector 1 is sent from the host side. In step S15, sector 1 is written into the flash memory. Processes for sending of sector 2 (step S16), writing of sector 2 (step S17), sending of sector 3 (step S18), and writing of sector 3 (step S19) are sequentially performed. Hitherto, for example, even if four storages are provided in parallel, since accesses are concentrated to one storage, a high processing speed cannot be realized.
As for a data construction of one sector on the flash memory, as shown in FIG. 18, an area having a length of 16 bytes in which management information is recorded is added to data of 512 bytes. The management information comprises a logic cluster number, cluster management information, and attribute information. The cluster management information is set to the same information among all sectors in a certain cluster and includes information indicative of “valid/invalid” of the cluster or the like. The attribute information is information of every sector and includes copyright information or the like. For example, when the flash memory is attached into the apparatus, the host side reads the management information and forms a table of the logic cluster and the physical cluster with respect to the segment.
In case of making a plurality of storages operative in parallel, it is necessary to consider a method of accessing to a plurality of storages. FIG. 19 shows a construction of supplying addresses to four storages. FIG. 20 shows addresses in a flash memory of 4 MB×4=16 MB. As described with reference to FIG. 14, the addresses are expressed by 11 bits of A0, A1, . . . , and A10. A0 is the LSB (least significant bit) and A10 is the MSB (most significant bit). The storages each having a capacity of 4 MB are switched by the MSB (A10) and the second MSB (A9). The addresses of 9 bits of A0 to A8 are allocated to the clusters in each storage.
Hitherto, to switch the four storages, the addresses are supplied to the flash memory as shown in FIG. 19. The addresses A0 to A8 of 9 bits on the lower side are allocated in common to the four storages (0 to 3). The addresses A9 and A10 of 2 bits on the upper side are supplied to a 2-to-4 decoder 60. Selection signals CS0, CS1, CS2, and CS3 for selecting the storages are generated from the decoder 60.
In case of (A10, A9)=00, the selection signal CS0 to select the storage 0 is generated from the decoder 60. When (A10, A9)=01, (A10, A9)=10, or (A10, A9)=11, each of the selection signals CS1, CS2, and CS3 for selecting each of the storage 1, storage 2, and storage 3 is generated from the decoder 60.
An address change at the time when the address is increased from a state where all of 11 bits are equal to 0 to a state where they are equal to 1 due to the switching of the storages as mentioned above is shown by arrows in FIG. 20. That is, when the address changes from the head cluster of the storage 0 to the final cluster of the storage 0, the cluster address changes so as to subsequently shift to the head cluster of the storage 1. FIG. 21 shows an arrangement of the segments and the logic cluster addresses.
In the conventional switching of the storages of the flash memory mentioned above, a storage selection signal is formed by using a few bits from the-MSB of the address. Thus, the segments are concentratedly arranged onto one storage and the segments are different every storage. According to such a method, a plurality of clusters of the same segment cannot be simultaneously written in parallel. For example, since four clusters (0x0004, 0x0005, 0x0006, 0x0007) in FIG. 21 are included in the same storage 0, they cannot be simultaneously written.
The clusters of a plurality of segments, for example, four clusters (0x0004, 0x0204, 0x0404, 0x0604) in FIG. 21 can be simultaneously written into the storages 0 to 3. However, according to the flash memory, since a logical/physical address conversion table is constructed every segment, it is necessary to refer to the logical/physical address conversion table upon accessing. Therefore, like an example mentioned above, when four clusters are simultaneously written over four segments, a memory for holding address conversion tables of four segments is needed. Each time the data of one sector is written into each segment, the necessity of referring to the address conversion table is caused. Performance upon writing (or upon reading) is deteriorated due to an overhead which is caused there.
It is, therefore, an object of the invention to provide a data processing system, a data processing apparatus, a memory apparatus, and a data recording method, in which data can be written in parallel into a plurality of storages and performance upon reading can be improved.